The present invention relates to a stuff synchronization circuit and, more particularly, to a stuff synchronization circuit in a pulse stuff synchronization system in which a plurality of asynchronous digital signals are multiplexed. The pulse stuff synchronization system serves to convert a digital signal of a clock frequency f.sub.L into a digital signal of a clock frequency f.sub.H which is asynchronous therewith. The clock frequency f.sub.H is higher than the clock frequency f.sub.L.
FIG. 1 shows a stuff synchronization circuit constituting a main component of a conventional pulse stuff synchronization system. An elastic memory 1 allows independent write and read access and has 8 bits. In response to a write clock signal 12 of a frequency f.sub.L, a writing counter 2 supplies write pulses W.sub.1 to W.sub.8 to the memory 1, for write-accessing the first to eighth bits of the elastic memory 1. A digital signal 10 is sequentially written at the first to eighth bit positions of the elastic memory 1 in accordance with the write pulses W.sub.1 to W.sub.8.
In response to a read clock signal 13 of a frequency f.sub.H, which is higher than the frequency f.sub.L, a reading counter 3 supplies read pulses R.sub.1 to R.sub.8 to the memory 1, for read-accessing the first to eighth bits of the elastic memory 1. Accordingly, the digital signal 10, which was written in the elastic memory 1 at the frequency f.sub.L, is read out as a digital signal 11 of the frequency f.sub.H.
Since the frequency f.sub.L of the write clock signal is lower than the frequency f.sub.H of the read clock signal, the write and read pulses for each bit will coincide periodically over the lapse of time. After a given coincidence of the write and read pulses, the timing of the succeeding read pulse will then become earlier than that of the write pulses, thereby causing a memory slip phenomenon in which a given data bit is read out twice prior to writing of the next data into that bit of the memory. According to the pulse stuff synchronization system, in order to prevent this memory slip phenomenon, one read access is delayed, and at the same time stuff bits are inserted at corresponding positions of the read signal 11. This operation is called stuffing. To perform the stuffing, the stuff synchronization circuit must detect the difference of between the write and read timings at a given time point (to be referred to as the phase comparison time point hereinafter) by detecting a phase difference between them.
In the stuff synchronization circuit in FIG. 1, a D flip-flop 4 serves to perform the above operation. A level of an output signal at a terminal Q of the D flip-flop 4 is set at "1" when an input signal to its terminal T rises while a level of an input signal at its terminal D is set at high level ("1"). The terminal D of the D flip-flop 4 receives the write pulse W.sub.1 for write-accessing the first bit of the elastic memory 1, and the terminal T receives the read pulse R.sub.1 for read-accessing the first bit of the elastic memory 1.
Since the level of the write pulse W.sub.1 is kept at "1" during one period (1 bit) of the write clock signal 12 of the frequency f.sub.L, if the phase difference between the write and read timings for accessing the first bit of the elastic memory 1 falls within one bit of the write pulse, the output from the terminal Q of the D flip-flop 4 is set at "1". In other words, the output from the D flip-flop 4 can be used for controlling stuffing. Outputs of levels "1" and "0" from the D flip-flop 4 represent the conditions that stuffing is required and not required, respectively.
A control bit such as a frame bit is normally added to the bits read out from the elastic memory 1, thereby constituting a frame. Generally, stuffing is only performed for a specific bit within a frame. A determination whether stuffing is to be performed in a frame is made at a specific time point (to be referred to as a stuff judgment time point hereinafter), e.g., at the start of the frame. When terminals D and T of a D flip-flop 5 in FIG. 1 respectively receive an output 15 from the terminal Q of the D flip-flop 4 and a signal 14 which rises at the start of each frame, a terminal Q of the D flip-flop 5 outputs a signal 16 which represents a determination made at the start of each frame, i.e., whether stuffing is to be performed or not. When it is set at "1", stuffing is performed, and when at "0", stuffing is not performed.
When stuff control is performed on the basis of a phase difference between the write and read timings of only one given bit in the conventional manner described above, the following problem is posed.
If f.sub.L =f.sub.H, a phase difference between the write and read timings for the first bit is equal to that between the write and read pulses for each of the other bits. In practice, however, since f.sub.L &lt;f.sub.H, the phase difference between the write and read timings becomes smaller as writing and reading are preformed from the first to eighth bits. When writing and reading are performed with respect to the first bit again, the phase difference becomes even smaller. Therefore, it is preferable to detect a phase difference is with respect to all the bits, and not limiting the detection to only one bit. In spite of the above fact, the stuff synchronization circuit having the arrangement shown in FIG. 1 is widely used. The reason for this is that it is difficult to obtain phase difference information, which varies over time, by detecting the phase difference between the write and read timings with respect to all of the bits.
In a stuff synchronization circuit of the type shown in FIG. 1, the intraframe number of the bit of the elastic memory 1 being written and read out at the stuff judgment time point, i.e., at the start of a frame, is not constant. In addition, the intraframe number of each bit varies in each frame. For example, when reading is performed with respect to the fifth bit of the memory at the stuff judgment time point the first bit in the frame, the phase comparison time point is positioned at a time point five bits before the stuff judgment time point. Accordingly, the stuff judgment is performed on the basis of the phase difference between the write and read timings for the first bit at the phase comparison time point. As a result, even if the phase difference between the write and read timings for the fifth bit is small enough to perform stuffing at the stuff judgment time point, stuffing may not be performed if the phase difference between the write and read timings is not so small at the phase comparison time point.
If a time interval between the stuff judgment time point and the phase comparison time point in each frame is constant, no problem is posed because it only means that the stuff judgment time point is equivalently shifted. In practice, however, the time interval between the stuff judgment time point and the phase comparison time point varies from frame to frame, so stuffing may or may not be performed in a frame in which stuffing should be performed. As a result, a very low frequency jitter is caused, as described in detail in U.S. Pat. No. 4,397,017. Since this very low frequency jitter is not easily removed, the performance of a system to which this pulse stuff synchronization system is applied is degraded.
According to a conventional method disclosed, e.g., in the above publication as a countermeasure against the jitter, the number of bits of the elastic memory 1 is carefully selected so as to minimize the amplitude of the very low frequency jitter. However, the method can only minimize the amplitude of the very low frequency jitter; it cannot prevent the very low frequency jitter.